1. Field of the Invention
The present invention relates to a repair circuit of a semiconductor memory device, such as a DRAM device, and more particularly to a repair circuit of a semiconductor memory device by which a defective cell is replaced with a redundant cell by programming an anti-fuse.
2. Discussion of the Related Art
If even one of a large number of defined cells in a semiconductor memory device is defective in its operation, the memory device as a whole must be treated as a defective (unusable) product, because the device cannot be normally operated as a dynamic random access memory (DRAM). It is, however, highly impractical to discard the entire memory device when only a very few of the defined cells are actually defective, which is especially true as the integration of a DRAM device increases. Therefore, when defective cells are present, which is an inevitable occurrence, such cells are replaced with spare or "redundant" memory cells. The redundant memory cells are embedded (pre-installed) within a manufactured DRAM device, in the form a redundancy circuit, for the express purpose of replacing all identified defective cells and thereby improving the yield of the final product.
The adverse result of this universal provision of redundant memory cells is an undesirable increase of the area of a given chip, which in turn increases the complexity of the test for identifying the defective cells themselves. Nevertheless, such a technique of installing a redundancy circuit is generally used in 64.about.256 Kb DRAMs as a standard practice, since the increased chip area is not excessive. Typically, a redundancy circuit for a memory cell is pre-installed in each sub-array block, whereby spare rows and columns are established, thereby enabling the replacement of each defective cell with a redundant memory cell in a row/column when cell defects are identified.
To identify the defective memory cells, an electrical test is performed to check each memory cell of every memory device of a completed wafer. Then, the memory devices are "reprogrammed" using a repair circuit to effectively change the addresses of the defective cells, such that when the address signal for a defective cell is selected, a spare (replacement) cell is internally addressed in its place. In doing so, when the defective addresses are input to the memory device during its actual operation, pre-installed alternative address lines are selected instead of the addresses originally corresponding to defective lines.
Such a programming method can be achieved by one of several methods: by burning open a pre-installed fuse using a current overload, as an ordinary electrical fuse; using a laser beam to cut traces (polysilicon or metal wirings) in order to create an electrical open or an electrical short; or by programming an EPROM memory cell. Among these methods, the laser cutting method is simple and precise and therefore widely used.
FIG. 1 is a circuit diagram illustrating a repair circuit for repairing defective elements (cells) using an ordinary fuse. The repair circuit comprises an operation switch 110 for performing a charging function in response to a charge/discharge signal; an address input unit 120 comprised of a plurality of NMOS transistors connected via a plurality of parallel polysilicon fuses 140 between the operation switch and ground, to respond to an address signal made up of a plurality of address lines, in order to detect the cutting state of the polysilicon fuses; and an output unit 130 comprised of an invertor, connected to the common node of the operation switch and the fuses, for outputting a repair value voltage in accordance with the charged state of the circuit and the status of the polysilicon fuses.
In the operation of the repair circuit constructed as above, when the charge signal is at a low potential, the operation switch 110 is turned-on, thereby applying the supply voltage (Vcc) potential to the polysilicon fuses 140. In this state, as each line of the input address signal is driven at a high potential to turn on the corresponding NMOS transistor, the supply voltage is supplied from the operation switch 110 to ground via the turned-on transistor and its corresponding fuse, so that the potential at a node "a" is held low for each address line test. This low level of electric potential is inverted and output by the output unit 130 as a repair value. Accordingly, the repair value is normally high.
On the other hand, when a polysilicon fuse is cut with a laser beam, the corresponding current path between the operation switch 110 and the address input unit 120 is interrupted, so that when the address line test is performed as above, the potential at the node "a" stays high (charged). Accordingly, the inverted, low-level repair value signal output by the output unit 130 indicates an identifiable cut fuse.
Thus, if the repair value is low, indicating a programmed fuse, and an address designating a defective cell is input to the memory device, the defective cell is replaced by a redundant cell. In doing so, normal operation is achieved so that the memory device operates properly.
There are, however, several disadvantages in adopting a repair circuit as described above. For example, though laser technology is highly precise, cuttable fuses made of polysilicon are relatively large. Also, in cutting the polysilicon fuses using a laser beam, errors may occur in applying the laser beam to the target fuse, whereby the incomplete or unintended cutting of a fuse may result. In addition to such unreliability, laser cutting is a time-consuming operation, which increases manufacturing cost, that is, because defective cells cannot be repaired at the package level. Furthermore, as mentioned above, as semiconductor processing improves to increase integration and memory capacity, the occupying area of the larger number of polysilicon fuses increases as well, so that overall chip size must also increase. The increased memory capacity of a given chip necessitates much more time to repair the chip, thereby increasing manufacturing cost. Meanwhile, since the repair procedure of cutting a fuse with a laser beam must, inherently, be performed before the chip is packaged, a defect resulting from burn-in testing after chip packaging is completed cannot be repaired.
In order to resolve these problems, an anti-fuse, which is electrically programmed without using a fuse in the standard sense, has been introduced. The anti-fuse (also known as a diode fuse) is a fuse in which resistive isolation, determined by an insulation layer between a pair of electrodes, can be broken down by a low voltage, i.e., lower than that which would normally break down the insulation, applied across the electrodes. In other words, a predetermined voltage applied across the terminals of an anti-fuse will produce a short circuit of very low resistance.
FIG. 2 is a circuit diagram illustrating a repair circuit for repairing a defective cell by using a typical anti-fuse. Though FIG. 2 shows but a single anti-fuse 240, the same principle maybe applied to any number of such fuses, and a plurality of such anti-fuses are intended to be represented.
The repair circuit comprises an operation switch 210 for performing a charge operation using a supply voltage (Vcc); an address input unit 220 connected via the anti-fuse 240 between the operation switch and ground, by which the anti-fuse is programmed in response to the input of a defective address; an output unit 230 for outputting the repair value as a programming state of the anti-fuse in response to the address signal; a latch 250 for stabilizing the voltage level at a node a.cent. in response to an inverted repair value signal REP from the output unit; and a high-voltage supply 260 for supplying a high voltage to the anti-fuse and thereby producing a short circuit (very low resistance).
In the above repair circuit, the anti-fuse 240 maintains its insulated state while only the supply voltage level is applied, but becomes a virtual short circuit should a high voltage be applied. That is, in a normal state, where no program signal is input, the supply voltage is supplied to a programming circuit (an anti-fuse and NMOS combination) through the operation switch 210, thereby charging the programming circuit. When a charge voltage is thus applied to the anti-fuses 240, the voltage at node a.cent. becomes destabilized, so that the latch 250, operating in response to the REP signal, stabilizes the input to the output unit 230. Upon input of the program signal under these conditions, a high voltage is supplied to the anti-fuse 240 via the high voltage supply 260, thus "programming" the anti-fuse by way of a breakdown of its insulating barrier.
Thereafter, when a defective address is input, the address input unit 220 is driven according to the programmed (shorted) state of the anti-fuse 240, thereby outputting the low-level repair value through the output unit 230. At the same time, a current path passing the high voltage through the high-voltage supply 260 is formed, but the current path is interrupted in response to the REP signal output from the output unit 230, thereby preventing unnecessary current consumption.
Utilizing such an anti-fuse allows an electrical repair to be performed. Thus, an expensive laser repair system is not needed and the repair can be performed after package is completed. In order to electrically break down the insulation layer of the anti-fuse 240, however, the application of a high voltage is needed. Accordingly, the gate of an input MOS transistor of the output unit 230 is likewise subject to a high voltage, and general MOS transistors cannot withstand such levels without severe stress and the associated degradation of circuit reliability. In addition, the additional circuitry necessary to generate the high voltage for programming 2,000-5,000 anti-fuses, an ordinary number in such applications, greatly increases the required area of a memory device.